Modern integrated circuits generally contain several layers of interconnect structures fabricated above a substrate. The substrate may have active devices and/or conductors that are connected by the interconnect structure.
Interconnect structures, typically comprising trenches and vias, are usually fabricated in, or on, an interlayer dielectric (ILD). It is generally accepted that, the dielectric material in each ILD should have a low dielectric constant (k) to obtain low capacitance between conductors. Decreasing this capacitance between conductors, by using a low dielectric constant (k), results in several advantages. For instance, it provides reduced RC delay, reduced power dissipation, and reduced cross-talk between the metal lines.
Materials commonly used to achieve low k dielectrics/films are carbon doped oxides (CDOs) or amorphous CDOs. CDOs tend to have a k value less than 3.5, but suffer from weak mechanical properties. These weak mechanical properties often result in cracking of the CDO during high stress processing and packaging steps.
Another material that may be potentially used for ILDs is zeolite or silica zeolite. Zeolite material is advantageous in that they have high porosity and a relatively uniform pore distribution. Zeolite material also is known to have good mechanical strength. Furthermore, zeolite films have dielectric constants in the range of 2.7 and smaller. Yet, zeolite is a crystalline structure, which makes forming a uniform film extremely difficult.